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INTEGRATED CIRCUITS
DATA SHEET
UDA1361TS 96 kHz sampling 24-bit stereo audio ADC
Product specification Supersedes data of 2001 Jan 17 2002 Nov 25
Philips Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
FEATURES General * Low power consumption * 256, 384, 512 and 768fs system clock * 2.4 to 3.6 V power supply * Supports sampling frequency of 5 to 110 kHz * Small package size (SSOP16) * Integrated high-pass filter to cancel DC offset * Power-down mode * Supports 2 V (RMS) input signals * Easy application * Master or slave operation. Multiple format output interface * I2S-bus and MSB-justified format compatible * Up to 24 significant bits serial output. Advanced audio configuration * Stereo single-ended input configuration * High linearity, dynamic range and low distortion. ORDERING INFORMATION TYPE NUMBER UDA1361TS PACKAGE NAME SSOP16 DESCRIPTION GENERAL DESCRIPTION
UDA1361TS
The UDA1361TS is a single chip stereo Analog-to-Digital Converter (ADC) employing bitstream conversion techniques. The low power consumption and low voltage requirements make the device eminently suitable for use in low-voltage low-power portable digital audio equipment which incorporates recording functions. The UDA1361TS supports the I2S-bus data format and the MSB-justified data format with word lengths of up to 24 bits.
VERSION SOT369-1
plastic shrink small outline package; 16 leads; body width 4.4 mm
2002 Nov 25
2
Philips Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
QUICK REFERENCE DATA SYMBOL Supplies VDDA VDDD IDDA analog supply voltage digital supply voltage analog supply current fs = 48 kHz operating mode Power-down mode IDDD digital supply current fs = 48 kHz operating mode Power-down mode Tamb Analog Vi(rms) (THD + N)/S input voltage (RMS value) total harmonic distortion-plus-noise to signal ratio at 0 dB(FS) equivalent at -1 dB(FS) signal output fs = 48 kHz at -1 dB at -60 dB; A-weighted fs = 96 kHz at -1 dB at -60 dB; A-weighted S/N signal-to-noise ratio Vi = 0 V; A-weighted fs = 48 kHz fs = 96 kHz cs channel separation - - - - - - - - - 1.1 1.0 ambient temperature - - -40 3.5 - - 2.4 2.4 PARAMETER CONDITIONS MIN.
UDA1361TS
TYP.
MAX.
UNIT
3.0 3.0 10.5 0.5
3.6 3.6 - - - - +85 - - -83 -34 -80 -37 - - -
V V mA mA mA mA C V V dB dB dB dB dB dB dB
0.45 -
-88 -40 -85 -40 100 100 100
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Philips Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
BLOCK DIAGRAM
VDDA 16 VSSA 15 VRP 5 VRN 4 Vref 2
UDA1361TS
handbook, full pagewidth
SYSCLK 8 9 VDDD VSSD
UDA1361TS
1 ADC
10
VINL
14 DECIMATION FILTER VINR 3 ADC CLOCK CONTROL 7
MSSEL PWON
DATAO BCK WS
13 11 12 DIGITAL INTERFACE DC-CANCELLATION FILTER 6 SFOR
MGT451
Fig.1 Block diagram.
PINNING SYMBOL VINL Vref VINR VRN VRP SFOR PWON SYSCLK VDDD VSSD BCK WS DATAO MSSEL VSSA VDDA PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DESCRIPTION left channel input reference voltage right channel input negative reference voltage positive reference voltage data format selection input power control input system clock 256, 384, 512 or 768fs digital supply voltage digital ground bit clock input/output word select input/output data output master/slave select analog ground analog supply voltage Fig.2 Pin configuration.
handbook, halfpage
VINL 1 Vref 2 VINR 3 VRN 4
16 VDDA 15 VSSA 14 MSSEL 13 DATAO
UDA1361TS
VRP 5 SFOR 6 PWON 7 SYSCLK 8
MGT452
12 WS 11 BCK 10 VSSD 9 VDDD
2002 Nov 25
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Philips Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
FUNCTIONAL DESCRIPTION System clock The UDA1361TS accommodates master and slave modes. The system devices must provide the system clock regardless of master or slave mode. In the master mode a system clock frequency of 256fs is required. In the slave mode a system frequency of 256, 384, 512 or 768fs is automatically detected (for a system clock of 768fs the sampling frequency must be limited to 55 kHz). The system clock must be locked in frequency to the digital interface input signals. Input level The overall system gain is proportional to VDDA, or more accurately the potential difference between the reference voltages VVRP and VVRN. The -1 dB input level at which THD + N/S is specified corresponds to -1 dB(FS) digital output (relative to the full-scale swing). With an input gain switch, the input level can be calculated as follows: V VRP - V VRN at 0 dB gain: V i ( - 1 dB ) = --------------------------------- = V (RMS) 3 V VRP - V VRN at 6 dB gain: V i ( - 1 dB ) = --------------------------------- = V (RMS) 2x3 In applications where a 2 V (RMS) input signal is used, a 12 k resistor must be connected in series with the input of the ADC. This forms a voltage divider together with the internal ADC resistor and ensures that only 1 V (RMS) maximum is input to the IC. Using this application for a 2 V (RMS) input signal, the gain switch must be set to 0 dB. When a 1 V (RMS) input signal is input to the ADC in the same application the gain switch must be set to 6 dB. An overview of the maximum input voltage allowed against the presence of an external resistor and the setting of the gain switch is given in Table 1. The power supply voltage is assumed to be 3 V. Table 1
UDA1361TS
Application modes using input gain stage INPUT GAIN SWITCH 0 dB 0 dB 0 dB 6 dB MAXIMUM INPUT VOLTAGE (RMS) 2V 1V 1V 0.5 V
RESISTOR (12 k) Present Present Absent Absent
Multiple format output interface The serial interface provides the following data output formats in both master and slave modes (see Figs 3, 4 and 5): * I2S-bus with data word length of up to 24 bits * MSB-justified serial format with data word length of up to 24 bits. The master mode drives pins WS (word select; 1fs) and BCK (bit clock; 64fs). WS and BCK are received in slave mode. Table 2 Master/slave select MSSEL L H M Table 3 Select data format SFOR L H M Decimation filter The decimation from 64fs is performed in two stages. The first stage realizes a 4th-order sinx/x characteristic. This filter decreases the sample rate by 8. The second stage, a FIR filter, consists of 3 half-band filters, each decimating by a factor of 2. DATA FORMAT I2S-bus data format MSB-justified data format (reserved for analog test) MASTER/SLAVE SELECT slave mode master mode (reserved for digital test)
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Philips Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
Table 4 Decimation filter characteristic CONDITION 0 to 0.45fs >0.55 fs 0 to 0.45 fs VALUE (dB) 0.01 -0.2 -70 >135 Mute
UDA1361TS
ITEM Pass-band ripple Stop band Dynamic range
Pass-band droop 0.45fs
On recovery from Power-down, the serial data output DATAO is held LOW until valid data is available from the decimation filter. This time tracks with the sampling frequency: 12288 t = --------------- , t = 256 ms when fs = 48 kHz. fs Power-down mode/input voltage control The PWON pin can control the power saving together with the optional gain switch for 2 or 1 V (RMS) input. The UDA1361TS supports 2 V (RMS) input using a series resistor of 12 k. For the definition of the pin settings for 1 or 2 V (RMS) mode, it is assumed that this resistor is present as a default component. Table 6 Power-down/input voltage control PWON L M H POWER-DOWN OR GAIN Power-down mode 0 dB gain 6 dB gain
DC cancellation filter A IIR high-pass filter is provided to remove unwanted DC components. The filter characteristics are given in Table 5. Table 5 DC cancellation filter characteristic CONDITION - - at 0.00045fs at 0.00000036fs 0 to 0.45fs 0 -0.031 >40 >135 VALUE (dB) none
ITEM Pass-band ripple Pass-band gain Droop Attenuation at DC Dynamic range
Serial interface formats
handbook, full pagewidth WS
LEFT 1 2 3 8 1 2
RIGHT 3 8
BCK
DATA
MSB
B2
LSB
MSB
B2
LSB
MSB
INPUT FORMAT I2S-BUS
WS 1 BCK 2
LEFT 3 8 1 2
RIGHT 3 8
DATA
MSB
B2
LSB
MSB
B2
LSB
MSB
B2
MGT453
MSB-JUSTIFIED FORMAT
Fig.3 Serial interface formats.
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Philips Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDD Txtal(max) Tstg Tamb Ves supply voltage maximum crystal temperature storage temperature ambient temperature electrostatic handling voltage HBM; note 2 MM; note 2 Notes 1. All supply connections must be made to the same power supply. 2. ESD behaviour is tested in accordance with JEDEC II standard: PARAMETER note 1 CONDITIONS
UDA1361TS
MIN. - - -65 -40 -300
MAX. 4.0 150 +125 +85 +300
UNIT V C C C V
-3000 +3000 V
a) Human Body Model (HBM); equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor. b) Machine Model (MM); equivalent to discharging a 200 pF capacitor through a 0.75 H series inductor. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS VALUE 130 UNIT K/W
thermal resistance from junction to ambient in free air
DC CHARACTERISTICS VDDD = VDDA = 3 V; Tamb = 25 C; all voltages referenced to ground (pins 10 and 15); unless otherwise specified. SYMBOL Supplies VDDA VDDD IDDA analog supply voltage digital supply voltage analog supply current note 1 note 1 fs = 48 kHz operating mode fs = 96 kHz operating mode IDDD digital supply current fs = 48 kHz operating mode fs = 96 kHz operating mode - 7.0 0.65 - - mA mA Power-down mode - - 3.5 0.45 - - mA mA Power-down mode - - 10.5 0.5 - - mA mA Power-down mode - - 10.5 0.5 - - mA mA Power-down mode - 2.4 2.4 3.0 3.0 3.6 3.6 V V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
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Philips Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
UDA1361TS
SYMBOL
PARAMETER
CONDITIONS
MIN. - - - - - - - - - - - - - - -
TYP.
MAX.
UNIT
Digital input pin (SYSCLK) VIH VIL |ILI| Ci VIH VIM VIL VIH VIL |ILI| Ci VOH VOL VOH VOL Analog Vref Ri Ci Note 1. All power supply connections must be connected to the same external power supply unit. reference voltage input resistance input capacitance with respect to VSSA 0.45VDDA - - 0.5VDDA 12 20 0.55VDDA - - V k pF HIGH-level input voltage LOW-level input voltage input leakage current input capacitance 2.0 -0.5 - - 0.9VDD 0.4VDD -0.5 2.0 -0.5 - - IOH = -2 mA IOL = 2 mA IOH = -2 mA IOL = 2 mA 0.85VDDD - 0.85VDDD - 5.5 +0.8 1 10 V V A pF
Digital 3-level input pins (PWON, SFOR, MSSEL) HIGH-level input voltage MIDDLE-level input voltage LOW-level input voltage VDD + 0.5 0.6VDD +0.4 V V V
Digital input/output pins (BCK, WS) HIGH-level input voltage LOW-level input voltage input leakage current input capacitance HIGH-level output voltage LOW-level output voltage 5.5 +0.8 1 10 - 0.4 - 0.4 V V A pF V V
Digital output pin (DATAO) HIGH-level output voltage LOW-level output voltage V V
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Philips Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
UDA1361TS
AC CHARACTERISTICS (ANALOG) VDDD = VDDA = 3 V; fi = 1 kHz; Tamb = 25 C; all voltages referenced to ground (pins 10 and 15); unless otherwise specified. SYMBOL Vi(rms) Vi (THD + N)/S PARAMETER input voltage (RMS value) unbalance between channels total harmonic distortion-plus-noise to signal ratio fs = 48 kHz at -1 dB at -60 dB; A-weighted fs = 96 kHz at -1 dB at -60 dB; A-weighted S/N signal-to-noise ratio Vi = 0 V; A-weighted fs = 48 kHz fs = 96 kHz cs PSRR channel separation power supply rejection ratio fripple = 1 kHz; Vripple = 30 mV (p-p) 100 100 100 30 - - - - dB dB dB dB -85 -40 -80 -37 dB dB -88 -40 -83 -34 dB dB CONDITIONS at 0 dB(FS) equivalent at -1 dB(FS) signal output TYP. 1.1 1.0 <0.1 MAX. - - 0.4 UNIT V V dB
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Philips Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
UDA1361TS
AC CHARACTERISTICS (DIGITAL) VDDD = VDDA = 2.4 to 3.6 V; Tamb = -40 to +85 C; all voltages referenced to ground (pins 10 and 15); unless otherwise specified. SYMBOL System clock timing Tsys system clock cycle fsys = 256fs fsys = 384fs fsys = 512fs fsys = 768fs tCWL tCWH LOW-level system clock pulse width HIGH-level system clock pulse width 35 23 17 17 88 59 44 30 780 520 390 260 ns ns ns ns PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
0.40Tsys - 0.40Tsys - 64fs 1 f cy = ------- ; master mode T cy 1 f cy = ------- ; slave mode T cy - 50 50 - - - MSB-justified format - 0 - - 1 master mode slave mode slave mode -40 20 10 64fs - - - - - - - - - - 1 - - -
0.60Tsys ns 0.60Tsys ns 64fs 64fs - - 20 20 40 40 - 20 20 1 +40 - - Hz Hz ns ns ns ns ns ns ns ns ns fs ns ns ns
Serial data timing; see Figs 4 and 5 Tcy(CLK)(bit) bit clock period
tBCKH tBCKL tr tf
bit clock HIGH time bit clock LOW time rise time fall time
td(o)(D)(BCK) data output delay time (from BCK falling edge) td(o)(D)(WS) th(o)(D) tr(WS) tf(WS) fWS td(WS)(BCK) tsu(WS) th(WS) data output delay time (from WS edge) data output hold time word select rise time word select fall time word select period word select delay from BCK word select set-up time word select hold time
2002 Nov 25
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Philips Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
UDA1361TS
handbook, full pagewidth
WS
tr
t BCKH
tf
t d(WS)(BCK)
BCK t BCKL Tcy(CLK)(bit) DATAO
MGT454
t d(o)(D)(BCK) t h(o)(D)
Fig.4 Serial interface master mode timing.
handbook, full pagewidth
WS t h(WS) t su(WS)
tr
t BCKH
tf
BCK t BCKL Tcy(CLK)(bit) DATAO
MGT455
t d(o)(D)(WS)
t d(o)(D)(BCK) t h(o)(D)
Fig.5 Serial interface slave mode timing.
2002 Nov 25
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Philips Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
APPLICATION INFORMATION
UDA1361TS
The application information illustrated in Fig.6, is an optimum application environment. Simplification is possible at the cost of some performance degradation.
handbook, full pagewidth
C11 47 F (16 V)
X5 1 nF (63 V)
1
16 C6 47 F (16 V) C10 100 nF (63 V)
R3 1
VDDA
2 C3 47 F (16 V) C7 100 nF (63 V) C12 X6 1 nF (63 V) 47 F (16 V)
15 VDDD R7 47 k X3-1 X3-2 R6 47 k X3-3
3
14
4 C4 47 F (16 V) C8 100 nF (63 V) 5 VDDD X4-1 X4-2 VDDD X2-1 X2-2 X2-3 R5 47 k SYSCLK R10 47 R11 47 X4-3 R4 47 k 7 R13 47 k R12 47 k 6
13
X1-1 X1-2
UDA1361TS
12
X1-3 X1-4 X1-5 X1-6 X1-7 X1-8 11 X1-9 X1-10
VDDA
R1 220
10 C5 47 F (16 V) C9 100 nF (63 V)
8
9
R2 1
VDDD L1 BLM32A07 VDDD VDDA C2 100 F (16 V)
VD L2 BLM32A07 C1 100 F MGU297 (16 V)
The value of capacitors C11 and C12 can be reduced. Note that changing their value will change the cut-off frequency determined by the capacitor value and the12 k input resistance of the ADC.
Fig.6 Application diagram.
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Philips Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
PACKAGE OUTLINE SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm
UDA1361TS
SOT369-1
D
E
A X
c y HE vM A
Z
16
9
Q A2 pin 1 index A1 (A 3) Lp L A
1
e bp
8
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.5 A1 0.15 0.00 A2 1.4 1.2 A3 0.25 bp 0.32 0.20 c 0.25 0.13 D (1) 5.30 5.10 E (1) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1.0 Lp 0.75 0.45 Q 0.65 0.45 v 0.2 w 0.13 y 0.1 Z (1) 0.48 0.18 10 0o
o
Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT369-1 REFERENCES IEC JEDEC MO-152 EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 99-12-27
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Philips Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results:
UDA1361TS
* Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2002 Nov 25
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Philips Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not suitable(3)
UDA1361TS
SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable
suitable not not recommended(4)(5) recommended(6)
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
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Philips Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
UDA1361TS
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
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Philips Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
NOTES
UDA1361TS
2002 Nov 25
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Philips Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
NOTES
UDA1361TS
2002 Nov 25
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Philips Semiconductors
Product specification
96 kHz sampling 24-bit stereo audio ADC
NOTES
UDA1361TS
2002 Nov 25
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Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753503/02/pp20
Date of release: 2002
Nov 25
Document order number:
9397 750 10479

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